Compared with other display technologies, LED display has the advantages of self-illumination, excellent color reproduction, high refresh rate, power saving and easy maintenance. The high brightness and the large size of the splicing can be the decisive factor for the high growth of the LED display in the past two decades. In the field of large screen outdoor display, no other technology has been able to compete with LED display technology.
However, in the past, led display also has its shortcomings, such as large spacing between packaged lamp beads, resulting in lower resolution, not suitable for indoor and close-up viewing. In order to improve the resolution, it is necessary to reduce the spacing between the beads, but the size of the bead is reduced. Although the resolution of the whole screen can be improved, the cost will rise rapidly, and the excessive cost affects the large-scale commercial application of the small-pitch LED display. .
In recent years, with the efforts of chip manufacturing and packaging manufacturers, IC circuit manufacturers and screen manufacturers, the cost of single-package devices has become lower and lower, LED package devices have become smaller and smaller, and the pixel pitch of display screens has become smaller and smaller. The higher and higher resolution makes the advantage of the small-pitch LED display in the indoor large-screen display more and more obvious.
At present, small-pitch LEDs are mainly used in advertising media, sports venues, stage backgrounds, municipal engineering, etc., and continue to open up markets in the fields of transportation, broadcasting, and military. It is estimated that by 2018, the market size will be close to 10 billion. It can be predicted that in the next few years, the small-pitch LED display will continue to expand its market share and occupy the market space of DLP rear-projection. According to the China Everbright Securities Research Institute, by 2020, the replacement rate of DLP rear projections for small-pitch LED displays will reach 70% to 80%.
The author is engaged in the blue-green LED chip manufacturing industry and has been engaged in product development for many years. From the perspective of product design and process technology, the following discusses the requirements for the development of small-pitch LED displays for blue-green LED chips, and the possible solutions for chip ends.
Second, the small-pitch led display on the demand for LED chips
As the core of the LED display, the LED chip plays a vital role in the development of small-pitch LED. The current achievements and future development of small-pitch LED displays rely on the unremitting efforts of the chip.
On the one hand, the indoor display dot spacing has been gradually reduced from the early P4 to P1.5, P1.0, and P0.8 under development. Correspondingly, the lamp bead size has been reduced from 3535 to 2121 to 1010. Some manufacturers have developed 0808 and 0606 sizes, and even manufacturers are developing 0404 size.
It is well known that the size of a packaged bead is reduced, which inevitably requires a reduction in chip size. At present, the market size of blue-green chips for small-pitch display screens is about 30 mil2, and some chip factories are already producing 25 mil2 or even 20 mil2 chips.
On the other hand, the surface area of the chip becomes smaller, the brightness of the single core decreases, and a series of problems affecting the display quality become prominent.
The first is the requirement for grayscale. Unlike outdoor screens, the difficulty in indoor screen demand is not in brightness but in grayscale. At present, the brightness requirement of the indoor large-screen screen is about 1500 cd/m2 -2000 cd/m2, and the brightness of the small-pitch led display is generally about 600 cd/m2 -800 cd/m2, which is suitable for the long-term attention display. The brightness is about 100 cd/m2 -300 cd/m2.
One of the challenges of the current small-pitch LED screen is "low light and low gray". That is, the gray level is not enough at low brightness. To achieve "low light and high gray", the current solution for the package end is a black bracket. Since the black bracket is weak to the chip, the chip is required to have sufficient brightness.
The second is to show the problem of uniformity. Compared with the conventional screen, the pitch becomes smaller, and there are problems such as afterglow, first sweep darkness, low redness, and low gray unevenness. At present, for the problems of afterglow, first sweep darkness and low grayish redness, both the package end and the IC control end have made efforts to effectively alleviate these problems. The brightness uniformity problem under low gray scale is also corrected by point by point. The technology has eased. However, as one of the root causes of the problem, the chip side needs more effort. Specifically, the brightness uniformity at a small current is better, and the consistency of the parasitic capacitance is better.
The third is the reliability issue. The current industry standard is that the LED dead light rate is allowed to be one in ten thousand, which is obviously not suitable for small-pitch LED displays. Since the pixel density of the small-pitch screen is large and the viewing distance is close, if there is one dead light in 10,000, the effect is unacceptable. The future dead light rate needs to be controlled at one in 100,000 or even one in a million to meet the needs of long-term use.
In general, the development of small-pitch LEDs, the requirements for the chip segment are: size reduction, relative brightness improvement, good brightness consistency under small current, good parasitic capacitance consistency, and high reliability.
Third, the chip-side solution
1. Size reduction chip size reduction
On the surface, it is the problem of layout design, it seems that you can solve it by designing a smaller layout as needed. However, can the reduction in chip size continue indefinitely? the answer is negative. There are several reasons for limiting the size of the chip:
(1) Limitation of packaging processing. During the packaging process, two factors limit the size reduction of the chip. One is the restriction of the nozzle. The solid crystal needs to suck the chip, and the short side of the chip must be larger than the inner diameter of the nozzle. At present, the inner diameter of the nozzle with cost performance is about 80um. The second is the limitation of the wire bond. The first is that the wire spool, that is, the chip electrode must be large enough, otherwise the reliability of the wire can not be guaranteed, the industry reported that the minimum electrode diameter is 45um; secondly, the spacing between the electrodes must be large enough, otherwise the two wires will inevitably interfere with each other.
(2) Limitation of chip processing. There are also two limitations in the processing of the chip. One is the limitation of layout layout. In addition to the above limitations of the package end, electrode size, electrode spacing requirements, the electrode and MESA distance, the scribe line width, the boundary line spacing of different layers, etc. have their limitations, the chip's current characteristics, SD process capability, lithography processing capability The scope of the specific restrictions is determined. Generally, the minimum distance from the P electrode to the edge of the chip is limited to more than 14 μm.
The second is the limitation of the ability to cut processing. The SD dicing + mechanical splicing process has limits, and the chip size may be too small to rupture. As the wafer diameter increases from 2 inches to 4 inches, or increases to 6 inches in the future, the difficulty of dicing the lobes increases, that is, the size of the processable chip will increase. Taking a 4-inch film as an example, if the short side length of the chip is less than 90 μm and the aspect ratio is greater than 1.5:1, the yield loss will increase significantly.
Based on the above reasons, the author boldly predicts that after the chip size is reduced to 17mil2, the chip design and processing capability are close to the limit, and there is basically no room for reduction unless the chip technology solution has a big breakthrough.
2. Brightness improvement
Brightness enhancement is the eternal theme of the chip. The chip factory optimizes the internal quantum effect through epitaxial program optimization, and enhances the external quantum effect through chip structure adjustment.
However, on the one hand, the chip size reduction will inevitably lead to a reduction in the area of the light-emitting area and a decrease in the brightness of the chip On the other hand, the dot pitch of the small-pitch display is reduced, and the demand for brightness of the single chip is degraded. There is a complementary relationship between the two, but there is a bottom line. At present, in order to reduce costs, the chip end mainly performs subtraction on the structure, which usually pays the price of brightness reduction. Therefore, how to balance trade-offs is a problem that the operator should pay attention to.
3. Consistency at small currents
The so-called small current is compared with the current of conventional indoor and outdoor chip trials. As shown in the following figure, the chip I-V curve, the conventional indoor and outdoor chips work in the linear working area, and the current is large. The small-pitch LED chip needs to work in a non-linear working area close to 0, and the current is too small.
In the non-linear working area, the LED chip is affected by the semiconductor switching threshold, and the difference between the chips is more obvious. Analysis of the dispersion of brightness and wavelength for high-volume chips makes it easy to see that the discrete area of the nonlinear work area is much larger than the linear work area. This is an inherent challenge at the current chip end.
The first solution to this problem is the optimization of the extension direction to reduce the lower limit of the linear working area. Secondly, the optimization of the chip splitting is to distinguish the different characteristic chips.
4. Parasitic capacitance consistency
At present, there is no condition on the chip side to directly measure the capacitance characteristics of the chip. The relationship between capacitance characteristics and conventional measurement items is unclear and will be summarized by the industry. The direction of chip-side optimization is one-off adjustment, and the other is the refinement on the electrical binning, but the cost is high, not recommended.
Chip-side reliability can be described by various parameters during chip packaging and aging. But in general, the factors affecting the reliability of the chip after the screen are focused on ESD and IR.
ESD refers to the ability to resist static electricity. According to the IC industry, more than 50% of chip failures are related to ESD. To improve chip reliability, ESD capabilities must be improved. However, under the same epitaxial wafer and the same chip structure, the chip size becomes small, which inevitably leads to the weakening of the ESD capability. This is directly related to current density and chip capacitance characteristics and cannot be resisted.
IR refers to reverse leakage, which is usually measured at a fixed reverse voltage. IR reflects the number of internal defects in the chip. The larger the IR value, the more internal defects the chip has.
To improve ESD capability and IR performance, more optimizations must be made in terms of epitaxial structure and chip structure. In the case of chip binning, the strict ESD standard can effectively remove the ESD capability and the weak IR performance of the chip, thereby improving the reliability of the chip after the screen.
In summary, the author analyzes the series of challenges faced by the LED chip end with the development of small-pitch LED display screens, and gives improvement plans or directions one by one. It should be said that there is still a lot of room for optimization of LED chips. How to improve, but also the unemployed to develop their intelligence and continuous efforts.